1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a nonvolatile memory device and a method for operating the same.
2. Description of the Related Art
Since a nonvolatile memory device has both features of a random access memory (RAM), which can freely record and erase data, and features of a read only memory (ROM), which can retain stored data without supply of power, it may be used as a storage medium for a portable electronic device, such as a digital camera, a personal digital assistant (PDA), and an MP3 player.
A nonvolatile memory device often includes a plurality of nonvolatile memory cells which are electrically programmable and erasable. A basic structure of a single nonvolatile memory device includes a gate structure in which a floating gate and a control gate are stacked, a source, and a drain. The nonvolatile memory cell performs a program, erase or read operation by applying appropriate voltages to the control gate, the source, the drain, and a well.
A plurality of nonvolatile memory cells are grouped based on units of word lines and bit lines to constitute a memory cell array. The memory cell array is divided into a main cell array, a redundancy cell array, and a code address memory (CAM) cell array, depending on usage thereof.
The main cell array includes memory cells for performing program and erase operations, and the redundancy cell array includes redundancy cells for defective cells of the main cell array. The CAM cell array includes memory cells for storing information of normal cells or defective cells.
The operation of programming fault column address information of a conventional nonvolatile memory device into a CAM cell array is as follows.
Fault column address information FA1, FA2, FA3, . . . , FAn generated in a probe test is collected. The collected fault column address information FA1, FA2, FA3, FAn is programmed in a CAM cell array region of a NAND flash. At this time, the operation of programming the fault column address information FA1, FA2, FA3, . . . , FAn into the CAM cell array region is identical to the program operation of a nonvolatile memory device. That is, after the CAM cell array is erased, the collected fault column address information FA1, FA2, FA3, . . . , FAn is set to a page buffer corresponding to the erased CAM cell array and is programmed and stored in the corresponding CAM cell array.
When the probe test is completed, a wafer is packaged and a package test (PKT) is performed. At this time, since fault column address information FAK1, FAK2, FAK3, . . . , FAKm is additionally generated, the additionally generated fault column address information FAK1, FAK2, FAK3, . . . , FAKm should be programmed into the corresponding CAM cell array.
Therefore, the corresponding CAM cell array should be erased before the additionally generated fault column address information FAK1, FAK2, FAK3, . . . , FAKm is programmed in the corresponding CAM cell array. However, fault column address information FA1, FA2, FA3, . . . , FAn already generated in the probe test is programmed in the corresponding CAM cell array. Thus, if the corresponding CAM cell array is erased in order to store the fault column address information FAK1, FAK2, FAK3, . . . , FAKm additionally generated in the package test, the fault column address information FA1, FA2, FA3, . . . , FAn programmed in the probe test is erased.
Therefore, before the corresponding CAM cell array is erased, the fault column address information FA1, FA2, FA3, . . . , FAn generated in the probe test and programmed in the corresponding CAM cell array is to be read and stored in the memory of the test device.
After the fault column address information FA1, FA2, FA3, . . . , FAn generated in the probe test is stored in the memory of the test device and the corresponding CAM cell array is erased, the fault column address information FA1, FA2, FA3, . . . , FAn generated in the probe test and the fault column address information FAK1, FAK2, FAK3, . . . , FAKm generated in the package test are collected and stored in the page buffer corresponding to the erased CAM cell array and subsequently programmed and stored in the corresponding CAM cell array. In this manner, all fault address information generated in the nonvolatile memory device is finally stored in the corresponding CAM cell array.
However, in temporarily storing the fault column address information FA1, FA2, FA3, . . . , FAn, which is generated in the probe test and already programmed, in the test device in order to additionally program the fault column address information FAK1, FAK2, FAK3, . . . , FAKm generated in the package test, a heavy burden may be imposed on the operation of the test device using the finite memory.
Due to the burden imposed on the operation of the test device, more time may be taken to perform the test operation.